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2502es?avr?12/03 features high-performance, low-power avr ? 8-bit microcontroller advanced risc architecture ? 130 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier nonvolatile program and data memories ? 8k bytes of in-system self-programmable flash endurance: 10,000 write/erase cycles ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-write operation ? 512 bytes eeprom endurance: 100,000 write/erase cycles ? 512 bytes internal sram ? programming lock for software security peripheral features ? two 8-bit timer/counters with separate prescalers and compare modes ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? four pwm channels ? 8-channel, 10-bit adc 8 single-ended channels 7 differential channels for tqfp package only 2 differential channels with programmable gain at 1x, 10x, or 200x for tqfp package only ? byte-oriented two-wire serial interface ? programmable serial usart ? master/slave spi serial interface ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated rc oscillator ? external and internal interrupt sources ? six sleep modes: idle, adc noise reduction, power-save, power-down, standby and extended standby i/o and packages ? 32 programmable i/o lines ? 40-pin pdip, 44-lead tqfp, 44-lead plcc, and 44-pad mlf operating voltages ? 2.7 - 5.5v for ATMEGA8535l ? 4.5 - 5.5v for ATMEGA8535 speed grades ? 0 - 8 mhz for ATMEGA8535l ? 0 - 16 mhz for ATMEGA8535 8-bit microcontroller with 8k bytes in-system programmable flash ATMEGA8535 ATMEGA8535l preliminary summary rev. 2502es?avr?12/03 note: this is a summary document. a complete document is available on our web site at www.atmel.com.
2 ATMEGA8535(l) 2502es?avr?12/03 pin configurations figure 1. pinout ATMEGA8535 disclaimer typical values contained in this data sheet are based on simulations and characteriza- tion of other avr microcontrollers manufactured on the same process technology. min and max values will be available after the device is characterized. (xck/t0) pb0 (t1) pb1 (int2/ain0) pb2 (oc0/ain1) pb3 (ss) pb4 (mosi) pb5 (miso) pb6 (sck) pb7 reset vcc gnd xtal2 xtal1 (rxd) pd0 (txd) pd1 (int0) pd2 (int1) pd3 (oc1b) pd4 (oc1a) pd5 (icp1) pd6 pa0 (adc0) pa1 (adc1) pa2 (adc2) pa3 (adc3) pa4 (adc4) pa5 (adc5) pa6 (adc6) pa7 (adc7) aref gnd avcc pc7 (tosc2) pc6 (tosc1) pc5 pc4 pc3 pc2 pc1 (sda) pc0 (scl) pd7 (oc2) 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 (mosi) pb5 (miso) pb6 (sck) pb7 reset vcc gnd xtal2 xtal1 (rxd) pd0 (txd) pd1 (int0) pd2 pa4 (adc4) pa5 (adc5) pa6 (adc6) pa7 (adc7) aref gnd avcc pc7 (tosc2) pc6 (tosc1) pc5 pc4 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 (int1) pd3 (oc1b) pd4 (oc1a) pd5 (icp1) pd6 (oc2) pd7 vcc gnd (scl) pc0 (sda) pc1 pc2 pc3 pb4 (ss) pb3 (ain1/oc0) pb2 (ain0/int2) pb1 (t1) pb0 (xck/t0) gnd vcc pa0 (adc0) pa1 (adc1) pa2 (adc2) pa3 (adc3) 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 (mosi) pb5 (miso) pb6 (sck) pb7 reset vcc gnd xtal2 xtal1 (rxd) pd0 (txd) pd1 (int0) pd2 pa4 (adc4) pa5 (adc5) pa6 (adc6) pa7 (adc7) aref gnd avcc pc7 (tosc2) pc6 (tosc1) pc5 pc4 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 (int1) pd3 (oc1b) pd4 (oc1a) pd5 (icp1) pd6 (oc2) pd7 vcc gnd (scl) pc0 (sda) pc1 pc2 pc3 pb4 (ss) pb3 (ain1/oc0) pb2 (ain0/int2) pb1 (t1) pb0 (xck/t0) gnd vcc pa0 (adc0) pa1 (adc1) pa2 (adc2) pa3 (adc3) plcc note: mlf bottom pad should be soldered to ground.
3 ATMEGA8535(l) 2502es?avr?12/03 overview the ATMEGA8535 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing instructions in a single clock cycle, the ATMEGA8535 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. block diagram figure 2. block diagram internal oscillator oscillator watchdog timer mcu ctrl. & timing oscillator timers/ counters interrupt unit stack pointer eeprom sram status register usart program counter program flash instruction register instruction decoder programming logic spi adc interface comp. interface porta drivers/buffers porta digital interface general purpose registers x y z alu + - portc drivers/buffers portc digital interface portb digital interface portb drivers/buffers portd digital interface portd drivers/buffers xtal1 xtal2 reset control lines v cc gnd mux & adc aref pa0 - pa7 pc0 - pc7 pd0 - pd7 pb0 - pb7 avr cpu twi avcc internal calibrated oscillator
4 ATMEGA8535(l) 2502es?avr?12/03 the avr core combines a rich instruction set with 32 general purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the ATMEGA8535 provides the following features: 8k bytes of in-system programmable flash with read-while-write capabilities, 512 bytes eeprom, 512 bytes sram, 32 general purpose i/o lines, 32 general purpose working registers, three flexible timer/counters with compare modes, internal and external interrupts, a serial program- mable usart, a byte oriented two-wire serial interface, an 8-channel, 10-bit adc with optional differential input stage with progr ammable gain in tqfp package, a program- mable watchdog timer with internal oscillator, an spi serial port, and six software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port, and inte rrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc, to minimize switching noise during adc conversions. in standby mode, the crystal/ resonator oscillator is running while the rest of the device is sleeping. this allows very fast start-up combined with low-power consumption. in extended standby mode, both the main oscillator and the asynchro- nous timer continue to run. the device is manufactured using atmel?s high density nonvolatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on t he avr core. the boot program can use any interface to download the application program in the application flash memory. soft- ware in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel ATMEGA8535 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the ATMEGA8535 avr is supported with a full suite of program and system develop- ment tools including: c compilers, macro assemblers, program debugger/simulators, in- circuit emulators, and evaluation kits. at90s8535 compatibility the ATMEGA8535 provides all the features of the at90s8535. in addition, several new features are added. the ATMEGA8535 is backward compatible with at90s8535 in most cases. however, some incompatibilities between the two microcontrollers exist. to solve this problem, an at90s8535 compatibility mode can be selected by programming the s8535c fuse. ATMEGA8535 is pin compatible with at90s8535, and can replace the at90s8535 on current printed circuit boards. however, the location of fuse bits and the electrical characteristics differs between the two devices. at90s8535 compatibility mode programming the s8535c fuse will change the following functionality: the timed sequence for changing the watchdog time-out period is disabled. see ?timed sequences for changing the configuration of the watchdog timer? on page 43 for details. the double buffering of the usart receive register is disabled. see ?avr usart vs. avr uart ? compatibility? on page 143 for details.
5 ATMEGA8535(l) 2502es?avr?12/03 pin descriptions v cc digital supply voltage. gnd ground. port a (pa7..pa0) port a serves as the analog inputs to the a/d converter. port a also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. when pins pa0 to pa7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the ATMEGA8535 as listed on page 58. port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port c pins that are externally pulled low will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the ATMEGA8535 as listed on page 62. reset reset input. a low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running. the minimum pulse length is given in table 15 on page 35. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier. avc c avcc is the supply voltage pin for port a and the a/d converter. it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be con- nected to v cc through a low-pass filter. aref aref is the analog reference pin for the a/d converter.
6 ATMEGA8535(l) 2502es?avr?12/03 . register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f (0x5f) sreg i t h s v n z c 8 0x3e (0x5e) sph ? ? ? ? ? sp10 sp9 sp8 10 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 10 0x3c (0x5c) ocr0 timer/counter0 output compare register 83 0x3b (0x5b) gicr int1 int0 int2 ? ? ? ivsel ivce 47, 67 0x3a (0x5a) gifr intf1 intf0 intf2 ? ? ? ? ?68 0x39 (0x59) timsk ocie2 toie2 ticie1 ocie1a ocie1b toie1 ocie0 toie0 83, 113, 131 0x38 (0x58) tifr ocf2 tov2 icf1 ocf1a ocf1b tov1 ocf0 tov0 84, 114, 132 0x37 (0x57) spmcr spmie rwwsb ? rwwsre blbset pgwrt pgers spmen 225 0x36 (0x56) twcr twint twea twsta twsto twwc twen ?twie 178 0x35 (0x55) mcucr sm2 se sm1 sm0 isc11 isc10 isc01 isc00 30, 66 0x34 (0x54) mcucsr ?isc2 ? ? wdrf borf extrf porf 38, 67 0x33 (0x53) tccr0 foc0 wgm00 com01 com00 wgm01 cs02 cs01 cs00 81 0x32 (0x52) tcnt0 timer/counter0 (8 bits) 83 0x31 (0x51) osccal oscillator calibration register 28 0x30 (0x50) sfior adts2 adts1 adts0 ? acme pud psr2 psr10 57,86,133,200,220 0x2f (0x4f) tccr1a com1a1 com1a0 com1b1 com1b0 foc1a foc1b wgm11 wgm10 108 0x2e (0x4e) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 111 0x2d (0x4d) tcnt1h timer/counter1 ? counter register high byte 112 0x2c (0x4c) tcnt1l timer/counter1 ? counter register low byte 112 0x2b (0x4b) ocr1ah timer/counter1 ? output compare register a high byte 112 0x2a (0x4a) ocr1al timer/counter1 ? output compare register a low byte 112 0x29 (0x49) ocr1bh timer/counter1 ? output compare register b high byte 112 0x28 (0x48) ocr1bl timer/counter1 ? output compare register b low byte 112 0x27 (0x47) icr1h timer/counter1 ? input capture register high byte 112 0x26 (0x46) icr1l timer/counter1 ? input capture register low byte 112 0x25 (0x45) tccr2 foc2 wgm20 com21 com20 wgm21 cs22 cs21 cs20 126 0x24 (0x44) tcnt2 timer/counter2 (8 bits) 128 0x23 (0x43) ocr2 timer/counter2 output compare register 129 0x22 (0x42) assr ? ? ? ? as2 tcn2ub ocr2ub tcr2ub 129 0x21 (0x41) wdtcr ? ? ? wdce wde wdp2 wdp1 wdp0 40 0x20 (1) (0x40) (1) ubrrh ursel ? ? ? ubrr[11:8] 166 ucsrc ursel umsel upm1 upm0 usbs ucsz1 ucsz0 ucpol 164 0x1f (0x3f) eearh ? ? ? ? ? ? ? eear8 17 0x1e (0x3e) eearl eeprom address register low byte 17 0x1d (0x3d) eedr eeprom data register 17 0x1c (0x3c) eecr ? ? ? ? eerie eemwe eewe eere 17 0x1b (0x3b) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 64 0x1a (0x3a) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 64 0x19 (0x39) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 64 0x18 (0x38) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 64 0x17 (0x37) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 64 0x16 (0x36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 65 0x15 (0x35) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 65 0x14 (0x34) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 65 0x13 (0x33) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 65 0x12 (0x32) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 65 0x11 (0x31) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 65 0x10 (0x30) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 65 0x0f (0x2f) spdr spi data register 140 0x0e (0x2e) spsr spif wcol ? ? ? ? ? spi2x 140 0x0d (0x2d) spcr spie spe dord mstr cpol cpha spr1 spr0 138 0x0c (0x2c) udr usart i/o data register 161 0x0b (0x2b) ucsra rxc txc udre fe dor pe u2x mpcm 162 0x0a (0x2a) ucsrb rxcie txcie udrie rxen txen ucsz2 rxb8 txb8 163 0x09 (0x29) ubrrl usart baud rate register low byte 166 0x08 (0x28) acsr acd acbg aco aci acie acic acis1 acis0 200 0x07 (0x27) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 216 0x06 (0x26) adcsra aden adsc adate adif adie adps2 adps1 adps0 218 0x05 (0x25) adch adc data register high byte 219 0x04 (0x24) adcl adc data register low byte 219 0x03 (0x23) twdr two-wire serial interface data register 180 0x02 (0x22) twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce 180 0x01 (0x21) twsr tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 180
7 ATMEGA8535(l) 2502es?avr?12/03 notes: 1. refer to the usart description for details on how to access ubrrh and ucsrc. 2. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. 3. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 0x00 (0x20) twbr two-wire serial interface bit rate register 178 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
8 ATMEGA8535(l) 2502es?avr?12/03 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? kz,n,v1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1 / 2 / 3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1 / 2 / 3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1 / 2 / 3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1 / 2 / 3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1 / 2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1 / 2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1 / 2 data transfer instructions
9 ATMEGA8535(l) 2502es?avr?12/03 mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 mcu control instructions nop no operation none 1 mnemonics operands description operation flags #clocks
10 ATMEGA8535(l) 2502es?avr?12/03 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
11 ATMEGA8535(l) 2502es?avr?12/03 ordering information note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. speed (mhz) power supply ordering code package (1) operation range 8 2.7 - 5.5v ATMEGA8535l-8ac ATMEGA8535l-8pc ATMEGA8535l-8jc ATMEGA8535l-8mc 44a 40p6 44j 44m1 commercial ( 0 c to 70 c) ATMEGA8535l-8ai ATMEGA8535l-8pi ATMEGA8535l-8ji ATMEGA8535l-8mi 44a 40p6 44j 44m1 industrial (-4 0 c to 85 c) 16 4.5 - 5.5v ATMEGA8535-16ac ATMEGA8535-16pc ATMEGA8535-16jc ATMEGA8535-16mc 44a 40p6 44j 44m1 commercial ( 0 c to 70 c) ATMEGA8535-16ai ATMEGA8535-16pi ATMEGA8535-16ji ATMEGA8535-16mi 44a 40p6 44j 44m1 industrial (-4 0 c to 85 c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 40p6 40-pin, 0.600? wide, plastic dual inline package (pdip) 44j 44-lead, plastic j-leaded chip carrier (plcc) 44m1-a 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, micro lead frame package (mlf)
12 ATMEGA8535(l) 2502es?avr?12/03 packaging information 44a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ
13 ATMEGA8535(l) 2502es?avr?12/03 40p6 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40p6 , 40-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 40p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0?~ 15? d e eb common dimensions (unit of measure = mm) symbol min nom max note a 4.826 a1 0.381 d 52.070 52.578 note 2 e 15.240 15.875 e1 13.462 13.970 note 2 b 0.356 0.559 b1 1.041 1.651 l 3.048 3.556 c 0.203 0.381 eb 15.494 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
14 ATMEGA8535(l) 2502es?avr?12/03 44j notes: 1. this package conforms to jedec reference ms-018, variation ac. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 17.399 ? 17.653 d1 16.510 ? 16.662 note 2 e 17.399 ? 17.653 e1 16.510 ? 16.662 note 2 d2/e2 14.986 ? 16.002 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-lead, plastic j-leaded chip carrier (plcc) b 44j 10/04/01 2325 orchard parkway san jose, ca 95131 title drawing no. r rev.
15 ATMEGA8535(l) 2502es?avr?12/03 44m1-a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44m1 , 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm micro lead frame package (mlf) c 44m1 01/15/03 common dimensions (unit of measure = mm) symbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 a3 0.25 ref b 0.18 0.23 0.30 d 7.00 bsc d2 5.00 5.20 5.40 e 7.00 bsc e2 5.00 5.20 5.40 e 0.50 bsc l 0.35 0.55 0.75 notes: 1. jedec standard mo-220, fig. 1 (saw singulation) vkkd-1. top view side view bottom view d e marked pin# 1 id e2 d2 b e pin #1 corner l a1 a3 a seating plane
16 ATMEGA8535(l) 2502es?avr?12/03 errata there are no errata for this revision of ATMEGA8535.
17 ATMEGA8535(l) 2502es?avr?12/03 datasheet change log for ATMEGA8535 please note that the referring page numbers in this section are referring to this docu- ment. the referring revision in this section are referring to the document revision. changes from rev. 2502d-09/03 to rev. 2502e-12/03 1. updated ?calibrated internal rc oscillator? on page 27. 2. added section ?errata? on page 16. changes from rev. 2502c-04/03 to rev. 2502d-09/03 1. removed ?advance information? and some tbd?s from the datasheet. 2. added note to ?pinout ATMEGA8535? on page 2. 3. updated ?reset characteristics? on page 35. 4. updated ?absolute maximum ratings? and ?dc characteristics? in ?electrical characteristics? on page 252. 5. updated table 111 on page 255. 6. updated ?adc characteristics ? preliminary data? on page 260. 7. updated ?ATMEGA8535 typical characteristics ? preliminary data? on page 263. 8. removed call and jmp instructions from code examples and ?instruction set summary? on page 8. changes from rev. 2502b-09/02 to rev. 2502c-04/03 1. updated ?packaging information? on page 12. 2. updated figure 1 on page 2, figure 84 on page 176, figure 85 on page 182, figure 87 on page 188, figure 98 on page 204. 3. added the section ?eeprom write during power-down sleep mode? on page 20. 4. removed the references to the application notes ?multi-purpose oscillator? and ?32 khz crystal oscillator?, which do not exist. 5. updated code examples on page 42. 6. removed adhsm bit. 7. renamed port d pin icp to icp1. see ?alternate functions of port d? on page 62. 8. added information about pwm symmetry for timer 0 on page 77 and timer 2 on page 124. 9. updated table 68 on page 166, table 75 on page 187, table 76 on page 190, table 77 on page 193, table 108 on page 250, table 113 on page 258. 10. updated description on ?bit 5 ? twsta: twi start condition bit? on page 179.
18 ATMEGA8535(l) 2502es?avr?12/03 11. updated the description in ?filling the temporary buffer (page loading)? and ?performing a page write? on page 228. 12. removed the section description in ?spi serial programming characteristics? on page 251. 13. updated ?electrical characteristics? on page 252. 14. updated ?adc characteristics ? preliminary data? on page 260. 14. updated ?register summary? on page 6. 15. various timer 1 corrections. 16. added wd_fuse period in table 108 on page 250. changes from rev. 2502a-06/02 to rev. 2502b-09/02 1. canged the endurance on the flash to 10,000 write/erase cycles.
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